With the advent of the computer age, electronic systems have become a staple of modern life, and some may even deem them a necessity. Part and parcel with this spread of technology comes an ever greater drive for more functionality from these electronic systems. A microcosm of this quest for increased functionality is the size and capacity of various semiconductor devices. From the 8 bit microprocessor of the original Apple I, through the 16 bit processors of the original IBM PC AT, to the current day, the processing power of semiconductors has grown while the size of these semiconductors has consistently been reduce. In fact, Moore's law recites that the number of transistors on a given size piece of silicon will double every 18 months.
As semiconductors have evolved into these complex systems, almost universally the connectivity and power requirements for these semiconductors have been increasing. In fact, the higher the clock frequency utilized with a semiconductor, the greater that semiconductor's power consumption (all other aspects being equal). Part and parcel, however, with the increase in power consumption and operating frequency is the countervailing tendency toward reduced operating voltages in semiconductors and thus, tighter noise budgets. As can be seen then, these requirements may be at odds with one another to a certain extent. In particular, increasing the power consumption of a semiconductor device usually results in more switching noise, which is less than desirable given a tighter noise budget.
Turning briefly to FIG. 1, one example of a semiconductor package 100 is depicted. Die 110 comprising an integrated circuit, such as a microprocessor, is attached to substrate 120. Ball grid array (BGA) balls 130 serve to couple die 110 to one or more power sources or signal input/output lines. Typically substrate 120, with which microprocessors or semiconductors are packaged, is made of organic material (such as epoxy resin). Substrate 120 may be fabricated using build-up technology, which enables higher wiring capability by having fine-line build-up layer(s) on both sides of a coarser core substrate. Typically, these layers or planes of substrate 120 are coupled to BGA balls 130 through the use of vias. These BGA balls 130 may then be coupled to a printed circuit board (PCB) which comprises, or is coupled to, one or more power supplies.
FIG. 2 depicts an embodiment of this type of power distribution network in more detail. Power supply 210 is coupled to PCB 220 in close proximity to one or more sides of package 100 open for a power distribution network. Current flows from power supply 210, through layers of PCB 220, to area of PCB 220 where balls 130 of BGA are coupled, through vias (not shown) attached to BGA balls 130 to planes of substrate 120 and eventually to die 110.
Package 100, and PCB 200 to which package 100 is coupled, may be composed of build-up layers, where one side of package 100 is utilized for a power distribution network. These layers may consist of planes in package 100 and layers comprising PCB 220 to which package 100 is attached. Power supply module 210 may supply current to die 110 (or an area of die 110) in the center of package 100. This current may pass from PCB 220 through plate through holes (PTHs) in the layers of PCB 220 to BGA balls 130 of package 110; current can then flow from BGA balls 130 to die 110 through planes of package 100 coupled to vias, which are, in turn, coupled to BGA balls 130.
As the functionality of the semiconductor device on die 110 increases, many functional blocks may be embedded in the semiconductor device. Each of these functional blocks (e.g. processor cores, register memory, different arithmetic logic units, controllers, etc.) may have different power requirements. In other words each functional block of logic may utilize a different operating voltage. In this case, the power distribution network associated with some of these functional blocks may be separate in die 110, package 100 or PCB 220 utilized in conjunction with package 100. In other words, the power supplies, lines, planes, vias etc. utilized to deliver power to one functional block of die 110 may be distinct from similar components utilized to deliver power to another functional block of die 110.
Recently, however, a new architecture has been developed for computer processors. Known as a multi-core architecture, this processor architecture may be comprised of multiple processor cores interconnected by an inter-chip bus. In cases such as this, if similar processor cores are utilized the power requirements for each of these processor cores may be substantially similar. As may be imagined, then, in such multi-core architectures it may not be necessary to have a distinct power distribution network for each of these processor cores. In fact, each of the processor cores of a multi-core architecture may share a power supply through a common power distribution network.
In many cases, however, use of shared power distribution networks in conjunction with blocks of similar functionality in a semiconductor device may result in undesirable switching noise in cases where one or more of the functional blocks is not fully active, as power may continue to be supplied to basically inactive components. This undesirable switching noise may interfere with the operation of other components of the semiconductor device.
As can be seen then, what is desired is a low noise power distribution network for use with a semiconductor device, where such a power distribution network may be used to supply power to one or more functional blocks of the semiconductor device.